Interactive computer systems simulation
CPU Simulator.
Walk a deliberately simplified Von Neumann-style accumulator CPU through fetch, decode and execute microsteps.
Intended stage: GCSE core to A level recap. Prerequisites: binary place value, hexadecimal notation and basic programming sequence, selection and iteration.
Teaching model
This simulator is a teaching model, not a replica of one commercial processor. Instructions and data share the same 16-word memory. Each memory word stores eight bits; the meaning of those bits depends on how the CPU fetches or uses them.
- Registers: PC and MAR are 4 bits; MDR, CIR and ACC are 8 bits.
- Arithmetic: ADD and SUB wrap modulo 256. The N flag reflects bit 7 of ACC and the Z flag is set only when ACC is zero.
- Privacy: programme source, input queue, CPU state and output stay in volatile browser memory and disappear on reload.
- Reality check: real processors have many more registers, addressing modes, buses, caches and control behaviours.
Fetch, decode and execute without JavaScript
The CPU repeatedly copies PC into MAR, reads Memory[MAR] through MDR, copies MDR into CIR, advances PC, decodes the instruction bits, and then runs the instruction. The Control Unit coordinates the register transfers, the ALU performs ADD and SUB, main memory stores both instructions and data, and input/output move values in and out of the model.
Instruction words use the upper four bits for the opcode and the lower four bits for the operand. For example, LDA 14 is stored as 00011110: opcode 0001 means LDA and operand 1110 means address 14. A DAT row stores a data word; if the CPU fetches that word it will still decode the bits as an instruction.
Learning outcomes: explain the role of CPU registers and buses, trace fetch-decode-execute micro-operations, interpret simple machine-code instructions, and reason about accumulator programmes, flags, branches and two's-complement interpretations.
CPU walkthrough
Choose a guided scenario or build a programme to generate the trace. Future states are not shown until reached.
Blank learner trace worksheet
Programme title:
| Step | Phase | Micro-operation | PC | MAR | MDR | CIR | ACC | Z | N | Memory/output notes | |
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Memory recording space:
Output recording space: